A superscalar SMT processor implements instruction-level parallelism within a single processor. More than one instruction may be executed during a clock cycle by simultaneously dispatching multiple instructions to different functional units on the processor. Each functional unit is not a separate processor core, but rather an execution resource within the processor, such as an arithmetic logic unit (ALU), a bit shifter, or a multiplier.
The overall efficiency of the superscalar processor may be improved through the use of an SMT core that permits a plurality of independent threads or processes to be executed simultaneously on a single processor core. The SMT core also permits simultaneous execution of multiple tasks on the single processor core with different Page tables, different Task state segments, different protection rings and different Input/Output (I/O) permissions for each of the tasks. The SMT may include one or more microprocessors operatively coupled to one or more memory management units. Depending upon the specific details of implementation for the microprocessor and the memory management unit, the features of different protection rings and different I/O permissions may or may not be provided. On a fundamental level, one may expect different tasks to be using different resources as the same time, but a guarding mechanism may not always be enforced. The SMT core is supported by an operating system that includes software for implementing one or more functions to be performed by the superscalar processor, such as scheduling tasks, executing applications, controlling peripherals, managing data storage, and controlling communication resources.
A real-time processor is required to operate in a deterministic manner. When a task is executed more than once, or on multiple occasions, there should be a minimal variation in the execution time of the task. The task may also have a real time deadline, which must be met and therefore may require higher levels of determinism to provide more predictable execution time. Many operating systems specify task-level timing protection. This requires a user to specify a maximum permissible duration of time for execution of a task. Tasks not completed within the permissible duration of time trigger an alarm. If a task-timing protection scheme is to operate successfully, the specified duration of time for the task should exceed the actual execution time by a minimal amount. When the operating system provides a significant amount of inherent indeterminism, it is very difficult to provide an appropriate time budget for task execution.
SMT cores are typically targeted at non-real-time applications. More recently, SMT cores have been introduced to real-time applications as a potential solution to manage the performance-to-power ratio of the processor. However, the introduction of SMT cores into real-time applications is often perceived as adding an additional degree of undesired indeterminism to task execution. This indeterminism is caused by the sharing of resources within the SMT core between two or more threads. The degree of dual-issue capabilities of a first thread may be heavily influenced by the activity of a second thread and the second thread's use of processor resources.
For at least these reasons, therefore, it would be advantageous if new or improved systems and methods for providing a task-triggered deterministic operational mode for the SMT core could be achieved that address one or more of the previously-discussed limitations or other limitations.